这篇教程C++ ADDR_4TH_CYCLE函数代码示例写得很实用，希望能帮到您。
本文整理汇总了C++中ADDR_4TH_CYCLE函数的典型用法代码示例。如果您正苦于以下问题：C++ ADDR_4TH_CYCLE函数的具体用法？C++ ADDR_4TH_CYCLE怎么用？C++ ADDR_4TH_CYCLE使用的例子？那么恭喜您, 这里精选的函数代码示例或许可以为您提供帮助。 在下文中一共展示了ADDR_4TH_CYCLE函数的7个代码示例，这些例子默认根据受欢迎程度排序。您可以为喜欢或者感觉有用的代码点赞，您的评价将有助于我们的系统推荐出更棒的C++代码示例。 示例1: HAL_NAND_Erase_Block/** * @brief NAND memory Block erase. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress: pointer to NAND address structure * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress){ uint32_t deviceaddress = 0; uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ deviceaddress = NAND_DEVICE; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Get tick */ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_TIMEOUT; } } /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
开发者ID:Archcady，项目名称:mbed-os，代码行数:65，
示例2: HAL_NAND_Read_ID/** * @brief Read the NAND memory electronic signature * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pNAND_ID: NAND ID structure * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID){ __IO uint32_t data = 0; uint32_t deviceaddress = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ if(hnand->Init.NandBank == FMC_NAND_BANK2) { deviceaddress = NAND_DEVICE1; } else { deviceaddress = NAND_DEVICE2; } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Send Read ID command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; /* Read the electronic signature from NAND flash */ data = *(__IO uint32_t *)deviceaddress; /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK;}
开发者ID:Wanghuaichen，项目名称:dt900，代码行数:55，
示例3: HAL_NAND_Erase_Block/** * @brief NAND memory Block erase * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress){ uint32_t DeviceAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ DeviceAddress = NAND_DEVICE; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); } *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
开发者ID:ASzz，项目名称:verisure1512，代码行数:52，
示例4: HAL_NAND_Write_SpareArea/** * @brief Write Spare area(s) to NAND memory. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress: pointer to NAND address structure * @param pBuffer: pointer to source buffer to write * @param NumSpareAreaTowrite: number of spare areas to write to block * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite){ __IO uint32_t index = 0; uint32_t tickstart = 0; uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; uint32_t addressoffset = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ deviceaddress = NAND_DEVICE; /* Update the FMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Save the content of pAddress as it will be modified */ nandaddress.Block = pAddress->Block; nandaddress.Page = pAddress->Page; nandaddress.Zone = pAddress->Zone; /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); /* Get the address offset */ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } /* Write data to memory */ for(; index < size; index++) { *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Get tick */ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } } /* Increment written spare areas number */ num_spare_area_written++; /* Decrement spare areas to write */ NumSpareAreaTowrite--; /* Increment the NAND address */ addressstatus = NAND_AddressIncrement(hnand, &nandaddress); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
开发者ID:Archcady，项目名称:mbed-os，代码行数:99，
示例5: HAL_NAND_Read_Page/** * @brief Read Page(s) from NAND memory block. * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress: pointer to NAND address structure * @param pBuffer: pointer to destination read buffer * @param NumPageToRead: number of pages to read from block * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead){ __IO uint32_t index = 0; uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; uint32_t addressoffset = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ deviceaddress = NAND_DEVICE; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Save the content of pAddress as it will be modified */ nandaddress.Block = pAddress->Block; nandaddress.Page = pAddress->Page; nandaddress.Zone = pAddress->Zone; /* Page(s) read loop */ while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); /* Get the address offset */ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); /* Send read page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; /* Get Data into Buffer */ for(; index < size; index++) { *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; } /* Increment read pages number */ numpagesread++; /* Decrement pages to read */ NumPageToRead--; /* Increment the NAND address */ addressstatus = NAND_AddressIncrement(hnand, &nandaddress); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK;}
开发者ID:Archcady，项目名称:mbed-os，代码行数:86，
示例6: HAL_NAND_Write_SpareArea/** * @brief Write Spare area(s) to NAND memory * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer : pointer to source buffer to write * @param NumSpareAreaTowrite : number of spare areas to write to block * @retval HAL status */HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite){ __IO uint32_t index = 0; uint32_t tickstart = 0; uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ deviceAddress = NAND_DEVICE; /* Update the FMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* NAND raw address calculation */ nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten); /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); __DSB(); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); __DSB(); } /* Write data to memory */ for(index = 0; index < size; index++) { *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; __DSB(); } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { /* Get tick */ tickstart = HAL_GetTick(); if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } } /* Increment written spare areas number */ numSpareAreaWritten++; /* Decrement spare areas to write */ NumSpareAreaTowrite--; /* Increment the NAND address */ nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize)); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK;}
开发者ID:peterliu2，项目名称:FreeRTOS，代码行数:89，
示例7: HAL_NAND_Read_SpareArea/** * @brief Read Spare area(s) from NAND memory * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer: pointer to source buffer to write * @param NumSpareAreaToRead: Number of spare area to read * @retval HAL status*/HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead){ __IO uint32_t index = 0; uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ deviceAddress = NAND_DEVICE; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* NAND raw address calculation */ nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Spare area(s) read loop */ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize)))) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead); /* Send read spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress); } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; /* Get Data into Buffer */ for(index = 0; index < size; index++) { *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress; } /* Increment read spare areas number */ numSpareAreaRead++; /* Decrement spare areas to read */ NumSpareAreaToRead--; /* Increment the NAND address */ nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize)); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK;}
开发者ID:peterliu2，项目名称:FreeRTOS，代码行数:75，
注：本文中的ADDR_4TH_CYCLE函数示例整理自Github/MSDocs等源码及文档管理平台，相关代码片段筛选自各路编程大神贡献的开源项目，源码版权归原作者所有，传播和使用请参考对应项目的License；未经允许，请勿转载。
C++ ADDR_SHIFT函数代码示例
C++ ADDR_3RD_CYCLE函数代码示例 |
