自学教程：C++ MDP3_REG_WRITE函数代码示例

static int mdp3_dmap_histo_reset(struct mdp3_dma *dma){	unsigned long flag;	int ret;	spin_lock_irqsave(&dma->histo_lock, flag);	init_completion(&dma->histo_comp);	mdp3_dma_clk_auto_gating(dma, 0);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_INTR_ENABLE, BIT(0)|BIT(1));	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_RESET_SEQ_START, 1);	wmb();	dma->histo_state = MDP3_DMA_HISTO_STATE_RESET;	spin_unlock_irqrestore(&dma->histo_lock, flag);	mdp3_dma_callback_enable(dma, MDP3_DMA_CALLBACK_TYPE_HIST_RESET_DONE);	ret = wait_for_completion_killable_timeout(&dma->histo_comp,				msecs_to_jiffies(DMA_HISTO_RESET_TIMEOUT_MS));	if (ret == 0) {		pr_err("mdp3_dmap_histo_reset time out/n");		ret = -ETIMEDOUT;	} else if (ret < 0) {		pr_err("mdp3_dmap_histo_reset interrupted/n");	} else {		ret = 0;	}	mdp3_dma_callback_disable(dma, MDP3_DMA_CALLBACK_TYPE_HIST_RESET_DONE);	mdp3_dma_clk_auto_gating(dma, 1);	return ret;}

static int mdp3_dmap_lut_config(struct mdp3_dma *dma,			struct mdp3_dma_lut_config *config,			struct mdp3_dma_lut *lut){	u32 cc_config, addr, color;	int i;	if (config->lut_enable && lut) {		addr = MDP3_REG_DMA_P_CSC_LUT1;		if (config->lut_sel)			addr = MDP3_REG_DMA_P_CSC_LUT2;		for (i = 0; i < MDP_LUT_SIZE; i++) {			color = lut->color0_lut[i] & 0xff;			color |= (lut->color1_lut[i] & 0xff) << 8;			color |= (lut->color2_lut[i] & 0xff) << 16;			MDP3_REG_WRITE(addr, color);			addr += 4;		}	}	cc_config = MDP3_REG_READ(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG);	cc_config &= DMA_LUT_CONFIG_MASK;	cc_config |= config->lut_enable;	cc_config |= config->lut_position << 4;	cc_config |= config->lut_sel << 10;	MDP3_REG_WRITE(MDP3_REG_DMA_P_COLOR_CORRECT_CONFIG, cc_config);	wmb();	dma->lut_config = *config;	return 0;}

static int mdp3_dma_stop(struct mdp3_dma *dma, struct mdp3_intf *intf){	int ret = 0;	u32 status, display_status_bit;	if (dma->dma_sel == MDP3_DMA_P)		display_status_bit = BIT(6);	else if (dma->dma_sel == MDP3_DMA_S)		display_status_bit = BIT(7);	else		return -EINVAL;	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_VIDEO)		display_status_bit |= BIT(11);	intf->stop(intf);	ret = readl_poll_timeout((mdp3_res->mdp_base + MDP3_REG_DISPLAY_STATUS),				status,				((status & display_status_bit) == 0),				DMA_STOP_POLL_SLEEP_US,				DMA_STOP_POLL_TIMEOUT_US);	mdp3_dma_callback_disable(dma, MDP3_DMA_CALLBACK_TYPE_VSYNC |					MDP3_DMA_CALLBACK_TYPE_DMA_DONE);	mdp3_irq_disable(MDP3_INTR_LCDC_UNDERFLOW);	MDP3_REG_WRITE(MDP3_REG_INTR_ENABLE, 0);	MDP3_REG_WRITE(MDP3_REG_INTR_CLEAR, 0xfffffff);	init_completion(&dma->dma_comp);	dma->vsync_client.handler = NULL;	return ret;}

static int mdp3_dmap_histo_config(struct mdp3_dma *dma,			struct mdp3_dma_histogram_config *histo_config){	unsigned long flag;	u32 histo_bit_mask, histo_control;	u32 histo_isr_mask = MDP3_DMA_P_HIST_INTR_HIST_DONE_BIT |			MDP3_DMA_P_HIST_INTR_RESET_DONE_BIT;	spin_lock_irqsave(&dma->histo_lock, flag);	if (histo_config->bit_mask_polarity)		histo_bit_mask = BIT(31);	histo_bit_mask |= histo_config->bit_mask;	if (histo_config->auto_clear_en)		histo_control = BIT(0);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_FRAME_CNT,			histo_config->frame_count);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_BIT_MASK, histo_bit_mask);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_CONTROL, histo_control);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_INTR_ENABLE, histo_isr_mask);	spin_unlock_irqrestore(&dma->histo_lock, flag);	dma->histogram_config = *histo_config;	return 0;}

static int mdp3_dmas_update(struct mdp3_dma *dma, void *buf,				struct mdp3_intf *intf){	unsigned long flag;	int cb_type = MDP3_DMA_CALLBACK_TYPE_VSYNC;	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {		cb_type |= MDP3_DMA_CALLBACK_TYPE_DMA_DONE;		if (intf->active)			wait_for_completion_killable(&dma->dma_comp);	}	spin_lock_irqsave(&dma->dma_lock, flag);	MDP3_REG_WRITE(MDP3_REG_DMA_S_IBUF_ADDR, (u32)buf);	dma->source_config.buf = buf;	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD)		MDP3_REG_WRITE(MDP3_REG_DMA_S_START, 1);	if (!intf->active) {		pr_debug("mdp3_dmap_update start interface/n");		intf->start(intf);	}	wmb();	init_completion(&dma->vsync_comp);	spin_unlock_irqrestore(&dma->dma_lock, flag);	mdp3_dma_callback_enable(dma, cb_type);	wait_for_completion_killable(&dma->vsync_comp);	return 0;}

static int mdp3_dmap_ccs_config(struct mdp3_dma *dma,			struct mdp3_dma_color_correct_config *config,			struct mdp3_dma_ccs *ccs){	int i;	u32 addr;	if (!ccs)		return -EINVAL;	if (config->ccs_enable) {		addr = MDP3_REG_DMA_P_CSC_MV1;		if (config->ccs_sel)			addr = MDP3_REG_DMA_P_CSC_MV2;		for (i = 0; i < 9; i++) {			MDP3_REG_WRITE(addr, ccs->mv[i]);			addr += 4;		}		addr = MDP3_REG_DMA_P_CSC_PRE_BV1;		if (config->pre_bias_sel)			addr = MDP3_REG_DMA_P_CSC_PRE_BV2;		for (i = 0; i < 3; i++) {			MDP3_REG_WRITE(addr, ccs->pre_bv[i]);			addr += 4;		}		addr = MDP3_REG_DMA_P_CSC_POST_BV1;		if (config->post_bias_sel)			addr = MDP3_REG_DMA_P_CSC_POST_BV2;		for (i = 0; i < 3; i++) {			MDP3_REG_WRITE(addr, ccs->post_bv[i]);			addr += 4;		}		addr = MDP3_REG_DMA_P_CSC_PRE_LV1;		if (config->pre_limit_sel)			addr = MDP3_REG_DMA_P_CSC_PRE_LV2;		for (i = 0; i < 6; i++) {			MDP3_REG_WRITE(addr, ccs->pre_lv[i]);			addr += 4;		}		addr = MDP3_REG_DMA_P_CSC_POST_LV1;		if (config->post_limit_sel)			addr = MDP3_REG_DMA_P_CSC_POST_LV2;		for (i = 0; i < 6; i++) {			MDP3_REG_WRITE(addr, ccs->post_lv[i]);			addr += 4;		}	}	dma->ccs_config = *config;	if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD)		mdp3_ccs_update(dma);	return 0;}

static int mdp3_dmap_update(struct mdp3_dma *dma, void *buf,				struct mdp3_intf *intf){	unsigned long flag;	int cb_type = MDP3_DMA_CALLBACK_TYPE_VSYNC;	int rc = 0;	pr_debug("mdp3_dmap_update/n");	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {		cb_type = MDP3_DMA_CALLBACK_TYPE_DMA_DONE;		if (intf->active) {			rc = wait_for_completion_timeout(&dma->dma_comp,				KOFF_TIMEOUT);			if (rc <= 0) {				WARN(1, "cmd kickoff timed out (%d)/n", rc);				rc = -1;			}		}	}	if (dma->update_src_cfg) {		if (dma->output_config.out_sel ==				 MDP3_DMA_OUTPUT_SEL_DSI_VIDEO && intf->active)			pr_err("configuring dma source while dma is active/n");		dma->dma_config_source(dma);		dma->update_src_cfg = false;	}	spin_lock_irqsave(&dma->dma_lock, flag);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)buf);	dma->source_config.buf = buf;	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {		mdp3_ccs_update(dma);		MDP3_REG_WRITE(MDP3_REG_DMA_P_START, 1);	}	if (!intf->active) {		pr_debug("mdp3_dmap_update start interface/n");		intf->start(intf);	}	mb();	dma->vsync_status = MDP3_REG_READ(MDP3_REG_INTR_STATUS) &		(1 << MDP3_INTR_LCDC_START_OF_FRAME);	init_completion(&dma->vsync_comp);	spin_unlock_irqrestore(&dma->dma_lock, flag);	mdp3_dma_callback_enable(dma, cb_type);	pr_debug("mdp3_dmap_update wait for vsync_comp in/n");	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_VIDEO) {		rc = wait_for_completion_timeout(&dma->vsync_comp,			KOFF_TIMEOUT);		if (rc <= 0)			rc = -1;	}	pr_debug("mdp3_dmap_update wait for vsync_comp out/n");	return rc;}

static void mdp3_dmas_config_source(struct mdp3_dma *dma){	struct mdp3_dma_source *source_config = &dma->source_config;	u32 dma_s_cfg_reg, dma_s_size;	dma_s_cfg_reg = MDP3_REG_READ(MDP3_REG_DMA_S_CONFIG);	dma_s_cfg_reg &= ~MDP3_DMA_IBUF_FORMAT_MASK;	dma_s_cfg_reg |= source_config->format << 25;	dma_s_size = source_config->width | (source_config->height << 16);	MDP3_REG_WRITE(MDP3_REG_DMA_S_CONFIG, dma_s_cfg_reg);	MDP3_REG_WRITE(MDP3_REG_DMA_S_SIZE, dma_s_size);	MDP3_REG_WRITE(MDP3_REG_DMA_S_IBUF_Y_STRIDE, source_config->stride);}

static void mdp3_hist_done_intr_handler(int type, void *arg){	struct mdp3_dma *dma = (struct mdp3_dma *)arg;	u32 isr, mask;	isr = MDP3_REG_READ(MDP3_REG_DMA_P_HIST_INTR_STATUS);	mask = MDP3_REG_READ(MDP3_REG_DMA_P_HIST_INTR_ENABLE);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_INTR_CLEAR, isr);	isr &= mask;	if (isr == 0)		return;	if (isr & MDP3_DMA_P_HIST_INTR_HIST_DONE_BIT) {		spin_lock(&dma->histo_lock);		dma->histo_state = MDP3_DMA_HISTO_STATE_READY;		complete(&dma->histo_comp);		spin_unlock(&dma->histo_lock);	}	if (isr & MDP3_DMA_P_HIST_INTR_RESET_DONE_BIT) {		spin_lock(&dma->histo_lock);		dma->histo_state = MDP3_DMA_HISTO_STATE_IDLE;		complete(&dma->histo_comp);		spin_unlock(&dma->histo_lock);	}}

static int mdp3_dmap_lut_config(struct mdp3_dma *dma,			struct mdp3_dma_lut_config *config,			struct mdp3_dma_lut *lut){	u32 addr, color;	int i;	if (config->lut_enable && lut) {		addr = MDP3_REG_DMA_P_CSC_LUT1;		if (config->lut_sel)			addr = MDP3_REG_DMA_P_CSC_LUT2;		for (i = 0; i < MDP_LUT_SIZE; i++) {			color = lut->color0_lut[i] & 0xff;			color |= (lut->color1_lut[i] & 0xff) << 8;			color |= (lut->color2_lut[i] & 0xff) << 16;			MDP3_REG_WRITE(addr, color);			addr += 4;		}	}	dma->lut_config = *config;	if (dma->output_config.out_sel != MDP3_DMA_OUTPUT_SEL_DSI_CMD)		mdp3_ccs_update(dma);	return 0;}

static void mdp3_dmap_config_source(struct mdp3_dma *dma){	struct mdp3_dma_source *source_config = &dma->source_config;	u32 dma_p_cfg_reg, dma_p_size;	dma_p_cfg_reg = MDP3_REG_READ(MDP3_REG_DMA_P_CONFIG);	dma_p_cfg_reg &= ~MDP3_DMA_IBUF_FORMAT_MASK;	dma_p_cfg_reg |= source_config->format << 25;	dma_p_cfg_reg &= ~MDP3_DMA_PACK_PATTERN_MASK;	dma_p_cfg_reg |= dma->output_config.pack_pattern << 8;	dma_p_size = source_config->width | (source_config->height << 16);	MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dma_p_cfg_reg);	MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, dma_p_size);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, source_config->stride);}

static int mdp3_dma_sync_config(struct mdp3_dma *dma,			struct mdp3_dma_source *source_config){	u32 sync_config;	int dma_sel = dma->dma_sel;	pr_debug("mdp3_dma_sync_config/n");	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {		int porch = source_config->vporch;		int height = source_config->height;		int vtotal = height + porch;		sync_config = vtotal << 21;		sync_config |= source_config->vsync_count;		sync_config |= BIT(19);		sync_config |= BIT(20);		MDP3_REG_WRITE(MDP3_REG_SYNC_CONFIG_0 + dma_sel, sync_config);		MDP3_REG_WRITE(MDP3_REG_VSYNC_SEL, 0x024);		MDP3_REG_WRITE(MDP3_REG_PRIMARY_VSYNC_INIT_VAL + dma_sel,				height);		MDP3_REG_WRITE(MDP3_REG_PRIMARY_RD_PTR_IRQ, 0x5);		MDP3_REG_WRITE(MDP3_REG_SYNC_THRESH_0 + dma_sel, (4 << 16 | 2));		MDP3_REG_WRITE(MDP3_REG_PRIMARY_START_P0S + dma_sel, porch);		MDP3_REG_WRITE(MDP3_REG_TEAR_CHECK_EN, 0x1);	}	return 0;}

static int mdp3_dmap_histo_stop(struct mdp3_dma *dma){	unsigned long flag;	int cb_type = MDP3_DMA_CALLBACK_TYPE_HIST_RESET_DONE |			MDP3_DMA_CALLBACK_TYPE_HIST_DONE;	spin_lock_irqsave(&dma->histo_lock, flag);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_CANCEL_REQ, 1);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_INTR_ENABLE, 0);	wmb();	dma->histo_state = MDP3_DMA_HISTO_STATE_IDLE;	spin_unlock_irqrestore(&dma->histo_lock, flag);	mdp3_dma_callback_disable(dma, cb_type);	return 0;}

static void mdp3_dma_clk_auto_gating(struct mdp3_dma *dma, int enable){	u32 cgc;	int clock_bit = 10;	clock_bit += dma->dma_sel;	if (enable) {		cgc = MDP3_REG_READ(MDP3_REG_CGC_EN);		cgc |= BIT(clock_bit);		MDP3_REG_WRITE(MDP3_REG_CGC_EN, cgc);	} else {		cgc = MDP3_REG_READ(MDP3_REG_CGC_EN);		cgc &= ~BIT(clock_bit);		MDP3_REG_WRITE(MDP3_REG_CGC_EN, cgc);	}}

static int mdp3_dmap_config(struct mdp3_dma *dma,			struct mdp3_dma_source *source_config,			struct mdp3_dma_output_config *output_config){	u32 dma_p_cfg_reg, dma_p_size, dma_p_out_xy;	dma_p_cfg_reg = source_config->format << 25;	if (output_config->dither_en)		dma_p_cfg_reg |= BIT(24);	dma_p_cfg_reg |= output_config->out_sel << 19;	dma_p_cfg_reg |= output_config->bit_mask_polarity << 18;	dma_p_cfg_reg |= output_config->color_components_flip << 14;	dma_p_cfg_reg |= output_config->pack_pattern << 8;	dma_p_cfg_reg |= output_config->pack_align << 7;	dma_p_cfg_reg |= output_config->color_comp_out_bits;	dma_p_size = source_config->width | (source_config->height << 16);	dma_p_out_xy = source_config->x | (source_config->y << 16);	MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dma_p_cfg_reg);	MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, dma_p_size);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)source_config->buf);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, source_config->stride);	MDP3_REG_WRITE(MDP3_REG_DMA_P_OUT_XY, dma_p_out_xy);	MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x40);	dma->source_config = *source_config;	dma->output_config = *output_config;	mdp3_dma_sync_config(dma, source_config);	mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);	mdp3_dma_callback_setup(dma);	return 0;}

static int mdp3_dma_sync_config(struct mdp3_dma *dma,			struct mdp3_dma_source *source_config){	u32 sync_config;	int dma_sel = dma->dma_sel;	pr_debug("mdp3_dma_sync_config/n");	if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {		sync_config = (source_config->height - 1) << 21;		sync_config |= source_config->vsync_count;		sync_config |= BIT(19);		sync_config |= BIT(20);		MDP3_REG_WRITE(MDP3_REG_SYNC_CONFIG_0 + dma_sel, sync_config);		MDP3_REG_WRITE(MDP3_REG_VSYNC_SEL, 0x024);		MDP3_REG_WRITE(MDP3_REG_PRIMARY_VSYNC_INIT_VAL + dma_sel, 0);		MDP3_REG_WRITE(MDP3_REG_SYNC_THRESH_0 + dma_sel, 0x00100000);		MDP3_REG_WRITE(MDP3_REG_PRIMARY_START_P0S + dma_sel, 0x0);	}	return 0;}

static int mdp3_dmap_config(struct mdp3_dma *dma,			struct mdp3_dma_source *source_config,			struct mdp3_dma_output_config *output_config){	u32 dma_p_cfg_reg, dma_p_size, dma_p_out_xy;	dma_p_cfg_reg = source_config->format << 25;	if (output_config->dither_en)		dma_p_cfg_reg |= BIT(24);	dma_p_cfg_reg |= output_config->out_sel << 19;	dma_p_cfg_reg |= output_config->bit_mask_polarity << 18;	dma_p_cfg_reg |= output_config->color_components_flip << 14;	dma_p_cfg_reg |= output_config->pack_pattern << 8;	dma_p_cfg_reg |= output_config->pack_align << 7;	dma_p_cfg_reg |= output_config->color_comp_out_bits;	dma_p_size = source_config->width | (source_config->height << 16);	dma_p_out_xy = source_config->x | (source_config->y << 16);	MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dma_p_cfg_reg);	MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, dma_p_size);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)source_config->buf);	MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, source_config->stride);	MDP3_REG_WRITE(MDP3_REG_DMA_P_OUT_XY, dma_p_out_xy);	/*	 * NOTE: MDP_DMA_P_FETCH_CFG: max_burst_size need to use value 4, not	 * the default 16 for MDP hang issue workaround	 */	//MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x20);    //to solve the blue flicker of display	MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x40);	MDP3_REG_WRITE(MDP3_REG_PRIMARY_RD_PTR_IRQ, 0x10);	dma->source_config = *source_config;	dma->output_config = *output_config;	mdp3_dma_sync_config(dma, source_config);	mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);	mdp3_dma_callback_setup(dma);	return 0;}

static int mdp3_dmap_histo_start(struct mdp3_dma *dma){	unsigned long flag;	if (dma->histo_state != MDP3_DMA_HISTO_STATE_IDLE)		return -EINVAL;	spin_lock_irqsave(&dma->histo_lock, flag);	init_completion(&dma->histo_comp);	MDP3_REG_WRITE(MDP3_REG_DMA_P_HIST_START, 1);	wmb();	dma->histo_state = MDP3_DMA_HISTO_STATE_START;	spin_unlock_irqrestore(&dma->histo_lock, flag);	mdp3_dma_callback_enable(dma, MDP3_DMA_CALLBACK_TYPE_HIST_DONE);	return 0;}

int mdp3_dma_sync_config(struct mdp3_dma *dma,	struct mdp3_dma_source *source_config, struct mdp3_tear_check *te){	u32 vsync_clk_speed_hz, vclks_line, cfg;	int porch = source_config->vporch;	int height = source_config->height;	int total_lines = height + porch;	int dma_sel = dma->dma_sel;	vsync_clk_speed_hz = MDP_VSYNC_CLK_RATE;	cfg = total_lines << VSYNC_TOTAL_LINES_SHIFT;	total_lines *= te->frame_rate;	vclks_line = (total_lines) ? vsync_clk_speed_hz / total_lines : 0;	cfg |= BIT(19);	if (te->hw_vsync_mode)		cfg |= BIT(20);	if (te->refx100) {		vclks_line = vclks_line * te->frame_rate *			100 / te->refx100;	} else {		pr_warn("refx100 cannot be zero! Use 6000 as default/n");		vclks_line = vclks_line * te->frame_rate *			100 / 6000;	}	cfg |= (vclks_line & VSYNC_COUNT_MASK);	MDP3_REG_WRITE(MDP3_REG_SYNC_CONFIG_0 + dma_sel, cfg);	MDP3_REG_WRITE(MDP3_REG_VSYNC_SEL, VSYNC_SELECT);	MDP3_REG_WRITE(MDP3_REG_PRIMARY_VSYNC_INIT_VAL + dma_sel,				te->vsync_init_val);	MDP3_REG_WRITE(MDP3_REG_PRIMARY_RD_PTR_IRQ, te->rd_ptr_irq);	MDP3_REG_WRITE(MDP3_REG_SYNC_THRESH_0 + dma_sel,		((te->sync_threshold_continue << VSYNC_THRESH_CONT_SHIFT) |				 te->sync_threshold_start));	MDP3_REG_WRITE(MDP3_REG_PRIMARY_START_P0S + dma_sel, te->start_pos);	MDP3_REG_WRITE(MDP3_REG_TEAR_CHECK_EN, te->tear_check_en);	return 0;}