自学教程：C++ MDP_OUTP函数代码示例

//.........这里部分代码省略.........	switch (mfd->panel_info.bpp) {	case 24:		dma2_cfg_reg |= DMA_DSTC0G_8BITS |		    DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;		break;	case 18:		dma2_cfg_reg |= DMA_DSTC0G_6BITS |		    DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;		break;	case 16:		dma2_cfg_reg |= DMA_DSTC0G_6BITS |		    DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;		break;	default:		printk(KERN_ERR "mdp lcdc can't support format %d bpp!/n",		       mfd->panel_info.bpp);		return -ENODEV;	}	/* DMA register config */	dma_base = DMA_P_BASE;#ifdef CONFIG_FB_MSM_MDP40	if (mfd->panel.type == HDMI_PANEL)		dma_base = DMA_E_BASE;#endif	/* starting address */	MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf);	/* active window width and height */	MDP_OUTP(MDP_BASE + dma_base + 0x4, ((fbi->var.yres) << 16) |						(fbi->var.xres));	/* buffer ystride */	MDP_OUTP(MDP_BASE + dma_base + 0xc, fbi->fix.line_length);	/* x/y coordinate = always 0 for lcdc */	MDP_OUTP(MDP_BASE + dma_base + 0x10, 0);	/* dma config */	curr = inpdw(MDP_BASE + DMA_P_BASE);	mask = 0x0FFFFFFF;	dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);	MDP_OUTP(MDP_BASE + dma_base, dma2_cfg_reg);	/*	 * LCDC timing setting	 */	h_back_porch = var->left_margin;	h_front_porch = var->right_margin;	v_back_porch = var->upper_margin;	v_front_porch = var->lower_margin;	hsync_pulse_width = var->hsync_len;	vsync_pulse_width = var->vsync_len;	lcdc_border_clr = mfd->panel_info.lcdc.border_clr;	lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;	lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;	lcdc_width = mfd->panel_info.xres;	lcdc_height = mfd->panel_info.yres;	lcdc_bpp = mfd->panel_info.bpp;	hsync_period =	    hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;

/* timing generator off */static void mdp4_dsi_video_tg_off(struct vsycn_ctrl *vctrl){	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); /* turn off timing generator */	/* some delay after turning off the tg */	msleep(20);}

//.........这里部分代码省略.........	mdp4_overlay_dmap_xy(pipe);	mdp4_overlay_dmap_cfg(mfd, 1);	mdp4_overlay_rgb_setup(pipe);	mdp4_mixer_stage_up(pipe);	mdp4_overlayproc_cfg(pipe);	/*	 * LCDC timing setting	 */	h_back_porch = var->left_margin;	h_front_porch = var->right_margin;	v_back_porch = var->upper_margin;	v_front_porch = var->lower_margin;	hsync_pulse_width = var->hsync_len;	vsync_pulse_width = var->vsync_len;	lcdc_border_clr = mfd->panel_info.lcdc.border_clr;	lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;	lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;	lcdc_width = mfd->panel_info.xres;	lcdc_height = mfd->panel_info.yres;	lcdc_bpp = mfd->panel_info.bpp;	hsync_period =	    hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;	hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;	hsync_start_x = hsync_pulse_width + h_back_porch;	hsync_end_x = hsync_period - h_front_porch - 1;	display_hctl = (hsync_end_x << 16) | hsync_start_x;	vsync_period =	    (vsync_pulse_width + v_back_porch + lcdc_height +	     v_front_porch) * hsync_period;	display_v_start =	    (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew;	display_v_end =	    vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1;	if (lcdc_width != var->xres) {		active_h_start = hsync_start_x + first_pixel_start_x;		active_h_end = active_h_start + var->xres - 1;		active_hctl =		    ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;	} else {		active_hctl = 0;	}	if (lcdc_height != var->yres) {		active_v_start =		    display_v_start + first_pixel_start_y * hsync_period;		active_v_end = active_v_start + (var->yres) * hsync_period - 1;		active_v_start |= ACTIVE_START_Y_EN;	} else {		active_v_start = 0;		active_v_end = 0;	}#ifdef CONFIG_FB_MSM_MDP40	hsync_polarity = 1;	vsync_polarity = 1;	lcdc_underflow_clr |= 0x80000000;	/* enable recovery */#else	hsync_polarity = 0;	vsync_polarity = 0;#endif	data_en_polarity = 0;	ctrl_polarity =	    (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x38, ctrl_polarity);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x1c, active_hctl);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x20, active_v_start);	MDP_OUTP(MDP_BASE + LCDC_BASE + 0x24, active_v_end);	ret = panel_next_on(pdev);	if (ret == 0) {		/* enable LCDC block */		MDP_OUTP(MDP_BASE + LCDC_BASE, 1);		mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);	}	/* MDP cmd block disable */	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);	return ret;}

void mdp_lcdc_update(struct msm_fb_data_type *mfd){	struct fb_info *fbi = mfd->fbi;	uint8 *buf;	int bpp;	unsigned long flag;	uint32 dma_base;	int irq_block = MDP_DMA2_TERM;#ifdef CONFIG_FB_MSM_MDP40	int intr = INTR_DMA_P_DONE;#endif	if (!mfd->panel_power_on)		return;	/* no need to power on cmd block since it's lcdc mode */	if (!mfd->ibuf.visible_swapped) {		bpp = fbi->var.bits_per_pixel / 8;		buf = (uint8 *) fbi->fix.smem_start;		buf += fbi->var.xoffset * bpp +		fbi->var.yoffset * fbi->fix.line_length;	} else {		/* we've done something to update the pointer. */		bpp =  mfd->ibuf.bpp;		buf = mfd->ibuf.buf;	}	dma_base = DMA_P_BASE;#ifdef CONFIG_FB_MSM_MDP40	if (mfd->panel.type == HDMI_PANEL) {		intr = INTR_DMA_E_DONE;		irq_block = MDP_DMA_E_TERM;		dma_base = DMA_E_BASE;	}#endif	/* starting address */	MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf);	/* enable LCDC irq */	spin_lock_irqsave(&mdp_spin_lock, flag);	mdp_enable_irq(irq_block);	INIT_COMPLETION(mfd->dma->comp);	mfd->dma->waiting = TRUE;#ifdef CONFIG_FB_MSM_MDP40	outp32(MDP_INTR_CLEAR, intr);	mdp_intr_mask |= intr;	outp32(MDP_INTR_ENABLE, mdp_intr_mask);#else	outp32(MDP_INTR_CLEAR, LCDC_FRAME_START);	mdp_intr_mask |= LCDC_FRAME_START;	outp32(MDP_INTR_ENABLE, mdp_intr_mask);#endif	spin_unlock_irqrestore(&mdp_spin_lock, flag);	if (mfd->ibuf.vsync_enable)		wait_for_completion_killable(&mfd->dma->comp);	mdp_disable_irq(irq_block);}

/* * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile * has enough space h * w * 3 * 2 */static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable){	unsigned long flag;	int cndx = 0;	struct vsycn_ctrl *vctrl;	struct mdp4_overlay_pipe *pipe;	vctrl = &vsync_ctrl_db[cndx];	pipe = vctrl->base_pipe;	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);	if (mfd->ov0_wb_buf->write_addr == 0) {		pr_info("%s: no blt_base assigned/n", __func__);		return;	}	spin_lock_irqsave(&vctrl->spin_lock, flag);	if (enable && pipe->ov_blt_addr == 0) {		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;		pipe->ov_cnt = 0;		pipe->dmap_cnt = 0;		vctrl->ov_koff = 0;		vctrl->ov_done = 0;		vctrl->blt_free = 0;		mdp4_stat.blt_dsi_video++;		vctrl->blt_change++;	} else if (enable == 0 && pipe->ov_blt_addr) {		pipe->ov_blt_addr = 0;		pipe->dma_blt_addr =  0;		vctrl->blt_free = 4;	/* 4 commits to free wb buf */		vctrl->blt_change++;	}	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x/n", __func__,		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);	if (!vctrl->blt_change) {		spin_unlock_irqrestore(&vctrl->spin_lock, flag);		return;	}	spin_unlock_irqrestore(&vctrl->spin_lock, flag);	if (vctrl->blt_ctrl == OVERLAY_BLT_SWITCH_TG_OFF) {		int tg_enabled;		pr_info("%s: blt enabled by switching TG off/n", __func__);		vctrl->blt_change = 0;		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;		if (tg_enabled) {			mdp4_dsi_video_wait4vsync(cndx);			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);			mdp4_dsi_video_wait4dmap_done(0);		}		mdp4_overlayproc_cfg(pipe);		mdp4_overlay_dmap_xy(pipe);		if (pipe->ov_blt_addr) {			mdp4_dsi_video_blt_ov_update(pipe);			pipe->ov_cnt++;			/* Prefill one frame */			vsync_irq_enable(INTR_OVERLAY0_DONE,						MDP_OVERLAY0_TERM);			/* kickoff overlay0 engine */			mdp4_stat.kickoff_ov0++;			vctrl->ov_koff++;	/* make up for prefill */			outpdw(MDP_BASE + 0x0004, 0);		}		if (tg_enabled) {			/*			 * need wait for more than 1 ms to			 * make sure lanes' fifo is empty and			 * lanes in stop state befroe reset			 * controller			 */			usleep(2000);			mipi_dsi_sw_reset();			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);		}	}}

void mdp_hw_init(void){	int i;	/* MDP cmd block enable */	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);	/* debug interface write access */	outpdw(MDP_BASE + 0x60, 1);	outp32(MDP_INTR_ENABLE, MDP_ANY_INTR_MASK);	outp32(MDP_EBI2_PORTMAP_MODE, 0x3);	outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8, 0x0);	outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc, 0x0);	outpdw(MDP_BASE + 0x60, 0x1);	mdp_load_lut_param();	/*	 * clear up unused fg/main registers	 */	/* comp.plane 2&3 ystride */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0120, 0x0);	/* unpacked pattern */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x012c, 0x0);	/* unpacked pattern */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0130, 0x0);	/* unpacked pattern */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0134, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0158, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x15c, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0160, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0170, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0174, 0x0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x017c, 0x0);	/* comp.plane 2 */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0114, 0x0);	/* comp.plane 3 */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x0118, 0x0);	/* clear up unused bg registers */	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8, 0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0, 0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc, 0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0, 0);	MDP_OUTP(MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4, 0);#ifndef CONFIG_FB_MSM_MDP22	MDP_OUTP(MDP_BASE + 0xE0000, 0);	MDP_OUTP(MDP_BASE + 0x100, 0xffffffff);	MDP_OUTP(MDP_BASE + 0x90070, 0);	MDP_OUTP(MDP_BASE + 0x94010, 1);	MDP_OUTP(MDP_BASE + 0x9401c, 2);	/* LGE_CHANGE_S	  * Change code to apply new LUT for display quality. 2010-08-03. [email
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